The present invention relates to electronic data processing, and more particularly concerns a floating-point processor whose operands have exponent parts which are offset from their true values by a fixed bias.
Floating-point numbers are stored in computers as a fraction (or mantissa) part and an exponent part. Fractions most often have an associated sign bit to indicate whether the fraction is positive or negative. Exponents, on the other hand, are commonly represented as positive numbers only, even though the actual exponent value can be negative as well as positive. This is accomplished by adding a bias value to the true exponent value. For example, an 8-bit exponent field can represent actual exponent values of -126 to +127 by adding a bias of 127, yielding stored values +2 to +253. (The stored values 0, 1, 254, and 255 signify error conditions.)
Biased exponents, however, have a disadvantage for multiplication and division operations. Since the operand exponents must be added together for multiplication, the exponent of the result contains twice the bias, and another operation si required to subtract out the extra bias amount. In division, the operand exponents are subtracted; the result exponent then has no bias, and another operation is required to add the bias back in.
Heretofore, bias adjustments for multiplication and division have been performed with another trip through the same arithmetic unit used for adding or subtracting the operand exponents. For example, a multiplication operation may add the operand exponents from two registers in a first clock cycle, and store the sum in one of the registers. In a second clock cycle, the sum and a constant bias value are gated through the same adder, and stored again in one of the registers. Another technique is to provide two cascaded arithmetic units, which requires a slower cycle time to accommodate the longer data paths.
The most obvious disadvantage of these techniques is the extra time they require--substantially double the time required for unbiased exponents. This extra time becomes especially significant in floating-point processors which can skip over zeros in an operand, and thus terminate early. It is also significant in a multiprocessor setting, where exception conditions in the exponent of the result must be known before another processor can be allowed to proceed; see, for example, the commonly assigned application Ser. No. 339,285, filed Apr. 17, 1989 by T. J. Beacom, et al., entitled "Overlapped Execution of Sequential Instructions from a Common Stream in Multiple Processors."
Another penalty is that the data paths, registers, adders, etc., must have extra bit positions to handle the largest possible "real" biased sum, plus an extra bias amount. Where more than one adder is used, it may remain in the data path for other operations, such as rounding and operand loading, where it is not needed, thus slowing these operations as well; the alternative, switching out the extra adder, requires more gating logic, control signals, and some amount of time.